Edge AI Hardware Lab
Research Field
Weison Lin obtained his Bachelor's and Master's degrees from the Computer Science and Engineering Department, National Taiwan Ocean University, Keelung, Taiwan, in 2015 and 2017. He worked as a teaching assistant at National Taiwan Ocean University, taught FPGA, VLSI design, and development subjects to undergraduate-level students, and supervised many final-year projects.
He acquired a PhD degree from the School of Engineering, University of Edinburgh, United Kingdom. He was doing a PhD project on edge AI accelerator architecture design related to reconfiguration and targeting harsh environments. He is also interested in topics such as smart wearable devices, low-power circuits, and FPGA systems.
The lab is developing an edge AI accelerator system with a user-friendly framework involving instruction sets and control software design. The team is also collaborating with an analogue team to develop mixed-signal edge AI devices. On the other hand, the team is also seeking a method to shorten the RTL design-to-market time by utilising machine learning. Overall, the interesting topics are listed below:
- Edge AI accelerator system development (Utilising FPGA or cell-based ASIC)
- Efficient software framework for edge AI accelerator (Utilising C or Python and Verilog)
- Digital circuit design to handle analogue input signals for AI computation
- Machine learning for RTL design
- Edge AI accelerator system development (Utilising FPGA or cell-based ASIC): Innovating hardware-efficient convolutional engines and pooling functions tailored for edge deployment.
- Efficient software framework for edge AI accelerator (Utilising C or Python and Verilog)
- Reconfigurable Computing Systems: Designing resource-aware reconfigurable hardware for flexible AI acceleration.
- AI-Powered Communication Hardware: High-performance neural network-based (e.g., SW-Net) hardware for MIMO communication receivers.
- Mission-Critical AIoT: Smart aquaculture applications, including ocean temperature early-warning systems and small-scale edge AI on ESP32.Mission-Critical AIoT: Smart aquaculture applications, including ocean temperature early-warning systems and small-scale edge AI on ESP32.
- Digital circuit design to handle analogue input signals for AI computation
- Machine learning for RTL design
- Underwater vision detection: Developing robust AI recognition systems for turbid underwater environments, focusing on real-time hardware acceleration.
- Ocean Surface temperature detection
Award and Experience:
- Nov. 2025 | Award of Excellence
Our undergraduate researcher, Miss Chen, received the "Award of Excellence" in the 2025 Summer Research Internship Program. - Sep. 2025 | International Conference Presentation
Prof. Lin mentored and led an undergraduate student, Mr Tsai, to Japan to present their research paper at a prestigious international conference.
Projects:
1. Current Research Projects (Ongoing)
- Industry-Academia Collaboration: "Edge AI Image Recognition for Underwater Environments" (2026-2027).
- University Excellence Initiative: Co-PI for "Cross-disciplinary Career-oriented Curriculum Map" focusing on Digital System Design and Implementation.
2. Pending / Upcoming High-Impact Projects
- NSTC Research Project (Under Review): "Resource-Aware Dynamically Reconfigurable Adder Tree and Accumulator Memory Modules for Edge AI Accelerators."
- Ministry of Education Teaching Practice Project (Under Review): "Enhancing AIoT Project Implementation and Academic Discourse for International Graduate Students."
PhD in Engineering, The University of Edinburgh, United Kingdom.
Job Description
The intern will support the research team in:
- Implementing digital logic modules using Verilog or SystemVerilog.
- Assisting in the synthesis and simulation of hardware designs to ensure timing closure and resource efficiency.
- Developing testbench environments to verify the functionality of On-Memory Computing alignment strategies.
- Collecting and preprocessing sensor data for AI model training and hardware validation.
Preferred Intern Educational Level
Preferred intern educational level Bachelor (Senior) / Master / PhD
Skill sets or Qualities
- Basic knowledge of Computer Architecture and Digital Logic Design.
- Familiarity with Hardware Description Languages (Verilog or SystemVerilog).
- Experience with C/C++ or Python for algorithm modelling is a plus.
- Highly motivated to learn FPGA development and AI hardware-software co-design.
- Ability to communicate and document research progress in English.